It analyses the instructions by looking at the inputs to each instruction. Do the inputs depend on output from one or mo

We are not quite done with this explanation, but this gives you a bit of a clue. Basically, you can have parallelism that the programmer must know or the kind which the CPU fakes to look as if everything is a single thread. However, behind the scenes, it is doing Out-of-Order black magic.

These are much more practical to work with for all the magic a CPU does to make stuff run in parallel. The reason is that micro-ops are very wide (contain a lot of bits) and can contain all sorts of meta-information. You cannot add that kind of information to an ARM or x86 instruction as it would:

Also, micro-ops are usually easier to work with for the CPU. Why? Because they each do one simple limited task. Regular ISA instructions can be more complex causing a bunch of stuff to happen and thus actually translate to multiple micro-ops.

For example, the add r4, r1, 5 instruction depends on input from r1 which is produced by mul r1, r2, r3 . We can chain together these relationships into long elaborate graphs that the CPU can work through. The nodes are the instructions and the edges are the registers connecting them.

You can think of this as when writing a program. You have a public API that needs to be stable and everybody uses. That is the ARM, x86, PowerPC, MIPS, etc. instruction sets. The micro-ops are basically the private APIs that are used to implement the public ones.

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th fast.ai works through callbacks. Import Fastdash. Define a Fastdash object using the model name, your account email ID, and password as the parameters. Pass the Fastdash object via callbacks in the fit() function. To get notified if your model crashes, add the fit() function under exception handling, and in the except, call the sendCrash() method.

The CPU can analyze such a graph of nodes and determine which instructions it can perform in parallel and where it needs to wait for the results from multiple dependent calculations before carrying on.

In my explanation of Out-of-Order execution (OoO) I skipped some important details, which need to be covered. Otherwise, it is not possible to understand why Apple is ahead of the game and Intel and AMD may not be able to catch up.

It is the superior Out-of-Order execution that is making the Firestorm cores on the M1 kick ass and take names. It is in fact much stronger than anything from Intel or AMD. Likely stronger than anybody else in the mainstream market.

However internally the CPU works on an entirely different instruction set invisible to the programmer. We call these micro-operations (micro-ops or μops). The ROB is full of these micro-ops.

The big “scratchpad” I talked about is actually called the Reorder Buffer (ROB), and it doesn’t contain normal machine code instructions. Not the ones that the CPU fetches from memory to execute. These are the instructions in the CPU Instruction Set Architecture (ISA). That is the kind of instructions that we call x86, ARM, PowerPC, etc.

For CISC CPUs there is usually no alternative but to use micro-ops otherwise the large complex CISC instructions would make pipelines and OoO next to impossible to achieve.

Many instructions will finish early but we cannot make their results official. We cannot commit them; otherwise, we supply the result in the wrong order. To the rest of the world, it has to look as if the instructions were carried out in the same sequence as they were issued.

It is because the ability to run fast depends on how quickly you can fill up the ROB with micro-ops and with how many. The more quickly you fill it up and the larger it is the more opportunities you are given to pick instructions you can execute in parallel and thus improve performance.

Machine code instructions are chopped into micro-ops by what we call an instruction decoder. If we have more decoders we can chop up more instructions in parallel and thus fill up the ROB faster.